The current research interests of our group can be best described by our 'Research Pyramid' as shown on the right.
Moore's Law, which predicts that the number of transistors on a chip will double every 18 months,
has become a principle for the IC industry in delivering more and more powerful semiconductor chips
at decreasing cost per transistor. However, there is plenty of but not unlimited room at the bottom.
Continuing evolution of electronics beyond the scaling limit requires revolutionary vision and broad thinking across disciplines.
In the post-CMOS era, there are great needs for novel devices, disruptive technologies, alternative computer architecture
and advanced materials.
Our lab is devoted to addressing some of the aforementioned issues. Specifically, we are focusing on emerging nanodevices such as
high performance resistive switching devices (memristors) and their working mechanisms, integrated nanosystems with applications in unconventional
computing and beyond, and enabling nanotechnologies such as 3D heterogeneous integration and high-rate nanofabrication techniques with single-digit resolution.
A few examples of our recent research achievements are introduced as follows, click the tabs for project details. Should you have any questions regarding our past and current work, please do not hesitate to email Dr. Xia .
Direct Visualization of Metallic Filament in VCM-type Memristors
Valence change mechanism memory (VCM) type of memristive devices based on transition metal oxides are the leading contenders for memory and computing applications. For a long time, the switching mechanism was attributed to the motion of oxygen anions (or equivalently oxygen vacancies) in such material systems.
We developed a Ta/HfO2/Pt memristive device (Figure a) with fast switching speed, record high endurance (120 billion cycles) (Figure b), reliable retention (extrapolated to be >> 10 years at 85 oC), multilevel capability and over a million (220) potentiation/depression epochs using electrical pulse trains (Figure c). More importantly, we studied the switching mechanism using scanning transmission electron microscopy (STEM) and electron energy loss spectroscopy (EELS), and attributed the switching to the composition modulation of a sub-10 nm Ta-rich O-deficient conduction channel (Figures d to f) by both anion and cation migration under electric field and thermal effect. The results strongly suggest that the reactive metal electrode in the oxide based memristors plays a much more important role than previously expected in determining the switching mechanism and device performance.
Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO2 Memristor. (a) TEM cross-section view of the Ta/HfO2/Pt device. The inset shows an optical top-view image of the device (scale bar: 50 µm). (b) 120 billion switching cycles have been demonstrated. (c) 220 potentiation/depression epochs achieved. (d) HAADF-STEM image shows a sub-10 nm conduction channel connecting Ta top and Pt bottom electrodes. (e) Comparison of core-loss EELS spectra collected at the pristine HfO2 layer, conduction channel region and Ta electrode. It indicates the conduction channel is Ta-rich. (f) O-K edge EELS spectra taken at three areas, which clearly show the conduction channel is also O-deficient. Further reading: Hao Jiang et al., "Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO2 Memristor", Sci. Rep.6, 28525 (2016). [Link].
Nanoscale Memristive RF Switches
Radio-frequency (RF) switch is a critical component to route high frequency signals in wireless communication systems and consumer electronics. Traditional RF switches based on silicon MOSFET and HEMT technologies are approaching the limits in scaling, bandwidth and power efficiency. Emerging devices built with MEMS and phase change materials either need high voltage or require a heating circuit to toggle between the ON and OFF states.
We developed a RF switch based on memristor technology. To achieve low ON state resistance and OFF state capacitance and hence a high cut off frequency, we built our device using a pair of metal wires (Ag as an active electrode for its low resistivity) that are separated by a nanometer scale air gap (air has small relative permittivity that is close to 1). A typical structure of our RF switch is shown in Figure a. The formation and rupture of a Ag filament within the nanoscale airgap are responsible for the ON and OFF switching. The device can be programmed using low voltages, it also exhibits high dynamic range (>1012) and low ON state resistance (Figure b). We measured the RF performance of the RF switch up to 110 GHz and demonstrated low insertion loss (0.3 dB at 40 GHz) and high isolation (30 dB at 40 GHz)(Figures c and d). The extracted RON, COFF and cutoff frequency are 3.60 ohm, 1.37 fF and 35.2 THz, respectively. The memristive RF switch also possesses competitive linearity and good power-handling capability .
First nanoscale memristive RF switch. (a) Cross-sectional SEM image of the device junction of the nanoscale memristive RF switch. Inset shows the geometry of the memristive RF device. (b) Typical I-V curves for the SET and RESET processes for the device. The ON/OFF ratio of the device is nearly 1012. (c) Typical transmission spectrum of a device at the ON state (solid blue line) with fittings from the equivalent circuit model (dashed red line). (d) The transmission spectrum for OFF state with isolation at 40 GHz measured of ~30 dB. The inset shows the device structure and the reference planes used for de-embedding.
Further reading: Shuang Pi, Mohammad Ghadiri-Sadrabadi, Joseph C. Bardin and Qiangfei Xia. "Nanoscale Memristive Radiofrequency Switches", Nature Communications 6, 7519 (2015). [Link].
Scaling of memristive devices and arrays
Building high density crossbar arrays of ultra-small memristive devices is critical for their applications in the next generation memory and unconventional computing. Although individual devices of sub-5 nm junction dimension have been reported, the fabrication, testing and operation of sub-10 nm memristors in a massively parallel crossbar array remain challenging.
We fabricated devices with 8 x 8 nm2 junction area in a crossbar array by using nanoimprint lithography (NIL). The 8 nm feature size on the template was achieved by shrinking the linewidth of a SiO2 nanowire arrays (50 nm half-pitch) in diluted hydro-fluoric acid (Figures a to h). The device fabrication were implemented in three steps: (1) making bottom electrode arrays by using NIL, RIE, metallization and liftoff; (2) depositing a layer of switching medium; (3) patterning of top electrode arrays using a similar procedure as in (1). Part of the device array is shown in Figure i. Our 8 nm memristive devices exhibited typical resistive switching behavior with ultra-low operation current (peak current of ~600 pA) (Figure j). This led to ultra-small power consumption per switching event at approximately 3 nanowatts.
Smallest memristive devices in a crossbar array. (a-h) Schematic illustration of the fabrication principle for silica imprint template with arrays of 8 nm nanowires. (i) SEM image of part of the cross-point memristive device array (TiO2 as the switching layer in this case) with junction area of 8 x 8 nm2. (j) Typical IV curves for the 8 nm device. Further reading: Shuang Pi, Peng Lin and Qiangfei Xia, "Cross point arrays of 8 nm x 8 nm memristive devices fabricated with nanoimprint lithography", Journal of Vacuum Science and Tehcnology B 31, 06FA02(2013). [Link].
Memristor/CMOS hybrid integrated circuits
One possible way to extend Moore's Law beyond the limits of transistor scaling is to obtain the equivalent circuit functionality using fewer devices or
components, i.e., get more computing per transistor on a chip. One proposal for achieving this end was the hybrid CMOL (CMOS/molecule) circuits and its
modified version, FPNI (field-programmable nanowire interconnect). Rather than relentlessly shrinking transistor sizes, these architecture separates the
logic elements from the data routing network by lifting the configuration bits, routing switches, and associated components out of the CMOS layer and
making them a part of the interconnect. Memristor cross bars can be fabricated directly above the CMOS circuits, and serve as the reconfigurable data routing network.
The concept of hybrid circuits is schematically shown in Fig. a. The memristor cross-bar layers were fabricated on top of a CMOS substrate and
connected to two sets of tungsten vias coming up from the CMOS through an area interconnect (pads). Images of a finished hybrid chip are shown
in Fig. b, with part of the memristors shown in the inset.
In operation, certain memristors were configured by the CMOS circuitry to be closed thus connecting components in the CMOS layer to synthesize
particular logic circuits in a field-programmable gate array (FPGA) fashion (Fig. c). Satisfactory operation was achieved and part of the results
are shown in Fig. d with equivalent circuits, the visualization of the digital results from the test system and the measured truth table for each gate.
The memristors were also able to be switched OFF so the logic gates can be used in other circuits.
The successful operation of the logic gates implies that (1) the memristors were configured correctly by the CMOS circuitry, (2) the transistors in
the CMOS layer were successfully connected using the configured memristors and could communicate to perform higher level functions, and (3) the
fabrication processes for building the memristor cross-bars did not disturb the underlying CMOS. This work has set a foundation for future hybrid
circuits that will involve memristors.
First hybrid memristor/CMOS circuit. (a) Conceptual illustration of the hybrid circuit,
(b) Images of a hybrid chip with the memristor crossbars built on top (inset shows SEM image of a fragment of the memristor
crossbar array); (c) Memristor/ CMOS layer fabric on a die. The purple dashed lines are configured memristors that connect
blue and red tungsten vias at CMOS layer. (d) Equivalent circuits and digital logic results from the chip tester.
NOT, AND, OR, NAND, NOR gates a D-type flip-flop were successfully configured. Further reading: Qiangfei Xia, W. Robinett, M. W. Cumbie, et al., "Memristor-CMOS hybrid integrated
circuits for reconfigurable logic", Nano Letters9, 3640-3645 (2009). [Link].
Forming-free memristive devices fabricated with 1 lithgraphy step
Memristive devices are non-volatile, two-terminal passive electronic circuit elements with a resistance that changes with the polarity and amplitude of the applied voltage. The high and low resistance states instead of charge storage are used to represent the logic 1s and 0s. As a result, these devices are immune to the quantum mechanics limit which is a problem for transistors. They are promising for the next generation universal memories, non-volatile logic, and neuromorphic computing.
The typical structure of a memristive device consists of a layer of switching material that is sandwiched between two electrodes. Two lithography steps are usually required to fabricate this structure, one for the bottom electrodes and the other for the top. During the processing, the critical interfaces between the switching material and the two electrodes were exposed and may be contaminated, degrading the device performance. Two lithography steps also increases the fabrication time and cost and lowers the throughput and yield.
We invented a novel cross-bar fabrication technique using only one lithography step for all three layers (two electrodes and the switching layer) that led to forming-free devices with much lower switching current. In the new approach (schematics shown on the Left picture), an imprint mold having cross-bar structures instead of nanowire arrays was used to pattern cross-bar-shaped trenches in the resist stack. Metal evaporation with an oblique angle was then carried out to make the bottom electrodes. Due to shadow effects, metal entered one trench but not the other. A switching layer was immediately coated using sputter-deposition. The top electrodes were deposited in an electron beam evaporator with shadow evaporations, followed by a liftoff process. With this approach, the critical interfaces between the switching material and the two electrodes were protected from contaminants such as wet chemicals, resists, charged particles during reactive ion etching (RIE). Devices fabricated with this technique exhibited forming-free non-volatile switching behavior with an ON/OFF ratio over 1000 (Right). The switching current was at nA scale, much lower than usually observed for similar devices fabricated using a multistep lithography process (uA).
Forming-free memristive devices fabricated with 1 litho step. (Left) Schematic illustration of the self-aligned fabrication process. Arrows in (c) and (e) indicate the shadow evaporation directions. (Right) Typical I-V curves of a forming free device with
nA operational current. The device exhibits non-volatile switching behavior with an ON/OFF ratio over 1000 at 1 V. Device size is 100 nm by 100 nm. Further reading: Qiangfei Xia, J. J. Yang, W. Wu, X. M. Li and R. S. Williams, "Self-aligned memristor cross-point
arrays fabricated with one nanoimprint lithography step", Nano Letters10, 2909-2914 (2010). [Link]
Facilities and Equipment
We are well-equipped with nanofabrication, electrical measurement and physical characterization
facilities for our research. Some of them are owned by our group, some are shared facilities on
campus that we have full access to. A list of most relevant equipment is on the next page.
We truly appreciate the generosity and foresight of all our sponsors!