The current research interests of our group can be best described by our 'Research Pyramid' as shown on the right.

Moore's Law, which predicts that the number of transistors on a chip will double every 18 months, has become a principle for the IC industry in delivering more and more powerful semiconductor chips at decreasing cost per transistor. However, there is plenty of but not unlimited room at the bottom. Continuing evolution of electronics beyond the scaling limit requires revolutionary vision and broad thinking across disciplines. In the post-CMOS era, there are great needs for novel devices, disruptive technologies, alternative computer architecture and advanced materials.

Our lab is devoted to addressing some of the aforementioned issues. Specifically, we are focusing on emerging nanodevices such as high performance resistive switching devices (memristors) and their working mechanisms, integrated nanosystems with applications in unconventional computing and beyond, and enabling nanotechnologies such as 3D heterogeneous integration and high-rate nanofabrication techniques with single-digit resolution.

We are well-equipped with nanofabrication, electrical measurement and physical characterization facilities for our research. Some of them are owned by our group, some are shared facilities on campus that we have full access to. A list of most relevant equipment is on the next page.

Below are a couple of examples of our past research achievements. Highlights of our current projects will be selectively posted here once published. Should you have any questions regarding our past and current work, please do not hesitate to email Dr. Xia.

One possible way to extend Moore's Law beyond the limits of transistor scaling is to obtain the equivalent circuit functionality using fewer devices or components, i.e., get more computing per transistor on a chip. One proposal for achieving this end was the hybrid CMOL (CMOS/molecule) circuits and its modified version, FPNI (field-programmable nanowire interconnect). Rather than relentlessly shrinking transistor sizes, these architecture separates the logic elements from the data routing network by lifting the configuration bits, routing switches, and associated components out of the CMOS layer and making them a part of the interconnect. Memristor cross bars can be fabricated directly above the CMOS circuits, and serve as the reconfigurable data routing network.

The concept of hybrid circuits is schematically shown in Fig. a. The memristor cross-bar layers were fabricated on top of a CMOS substrate and connected to two sets of tungsten vias coming up from the CMOS through an area interconnect (pads). Images of a finished hybrid chip are shown in Fig. b, with part of the memristors shown in the inset. In operation, certain memristors were configured by the CMOS circuitry to be closed thus connecting components in the CMOS layer to synthesize particular logic circuits in a field-programmable gate array (FPGA) fashion (Fig. c). Satisfactory operation was achieved and part of the results are shown in Fig. d with equivalent circuits, the visualization of the digital results from the test system and the measured truth table for each gate. The memristors were also able to be switched OFF so the logic gates can be used in other circuits.

The successful operation of the logic gates implies that (1) the memristors were configured correctly by the CMOS circuitry, (2) the transistors in the CMOS layer were successfully connected using the configured memristors and could communicate to perform higher level functions, and (3) the fabrication processes for building the memristor cross-bars did not disturb the underlying CMOS. This work has set a foundation for future hybrid circuits that will involve memristors.

Memristive devices are non-volatile, two-terminal passive electronic circuit elements with a resistance that changes with the polarity and amplitude of the applied voltage. The high and low resistance states instead of charge storage are used to represent the logic 1s and 0s. As a result, these devices are immune to the quantum mechanics limit which is a problem for transistors. They are promising for the next generation universal memories, non-volatile logic, and neuromorphic computing.

The typical structure of a memristive device consists of a layer of switching material that is sandwiched between two electrodes. Two lithography steps are usually required to fabricate this structure, one for the bottom electrodes and the other for the top. During the processing, the critical interfaces between the switching material and the two electrodes were exposed and may be contaminated, degrading the device performance. Two lithography steps also increases the fabrication time and cost and lowers the throughput and yield.

We invented a novel cross-bar fabrication technique using only one lithography step for all three layers (two electrodes and the switching layer) that led to forming-free devices with much lower switching current. In the new approach (schematics shown on the Left picture), an imprint mold having cross-bar structures instead of nanowire arrays was used to pattern cross-bar-shaped trenches in the resist stack. Metal evaporation with an oblique angle was then carried out to make the bottom electrodes. Due to shadow effects, metal entered one trench but not the other. A switching layer was immediately coated using sputter-deposition. The top electrodes were deposited in an electron beam evaporator with shadow evaporations, followed by a liftoff process. With this approach, the critical interfaces between the switching material and the two electrodes were protected from contaminants such as wet chemicals, resists, charged particles during reactive ion etching (RIE). Devices fabricated with this technique exhibited forming-free non-volatile switching behavior with an ON/OFF ratio over 1000 (Right). The switching current was at nA scale, much lower than usually observed for similar devices fabricated using a multistep lithography process (uA).